The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and apparatus for implementing a writing operation in Static Random Access Memory (SRAM) cells employing PFET pass gates.
A typical static random access memory (SRAM) cell includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value therein, which voltage value represents a logical data bit (e.g., xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. With CMOS (complementary metal oxide semiconductor) technology, the inverters further include a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as a latch which stores the data bit therein so long as power is supplied to the memory array. In a conventional six-transistor cell, a pair of access transistors or pass gates (when activated by a word line) selectively couple the inverters to a pair of complementary bit lines.
FIG. 1 illustrates a conventional SRAM cell structure 100 which represents a single memory cell included within a memory array arranged in rows and columns. The SRAM cell structure 100 includes a six-transistor memory cell 102 which is capable of storing a binary bit of information. Specifically, the memory cell includes a pair of cross-coupled, complementary metal oxide semiconductor (CMOS) inverters. One inverter includes an NFET storage transistor N1 and a PFET load transistor P1. Similarly, a second inverter includes an NFET storage transistor N2 and a PFET load transistor P2. Transistors P1 and P2 are often referred to as pull-up transistors because of their coupling to the voltage source VDD. Transistors N1 and N2 are similarly referred to as pull-down transistors because of their coupling to ground. The memory cell 102 further contains NMOS access transistors (i.e., pass gates) NL and NR serving as switches, each of which are coupled between the bistable circuit (P1, N1, P2 and N2) and a pair of complementary bit lines BL and BR, respectively. Pass gates NL and NR are activated by an appropriate signal generated on a wordline WL.
While conventional SRAM cells typically employ NFETs for the pass gates, PFET pass gates have also been proposed for better stability, lower power and a substantially higher density for multi-port layouts. As a consequence of better stability, however, some difficulties may be experienced in writing through a PFET port. With decreased conductivity of smaller PFET pass gates, it takes longer for the node voltage within the cell to be pulled high or low. For a specific type of CMOS technology where the threshold voltage (VT) is about the same for both PFETs and NFETs, a reverse beta ratio of at least 1.8 in the layout is desired in order to provide the SRAM cell with acceptable write performance under worst case conditions. The reverse beta ratio for a PFET pass gate is defined as the ratio of the (W/L) of the PFET pass gate over the (W/L) of the pull-down NFET. Moreover, a beta ratio for a conventional SRAM cell (the beta ratio being defined as the ratio of the (W/L) of the pull-down NFET over the (W/L) of the NFET pass gate) of at least 1.8 is needed for stability.
In an exemplary layout for an SRAM cell having PFET pass gates, a PFET pass gate may have a width W≈0.16 xcexcm and a length L≈0.08 xcexcm. For low power applications, a more desired PFET pass gate configuration would be to have devices with a narrower width and a longer channel (e.g., Wxe2x89xa60.11 xcexcm and Lxe2x89xa70.10 xcexcm) so that off currents in a standby mode may be minimized. However, if such PFET pass gate dimensions were so implemented, the pull-down NFET would be much longer in order to maintain a reverse beta ratio xe2x89xa72, and thus the corresponding overall cell size would be increased, perhaps by as much as 20%. In the meantime, the read performance of the cell would be degraded.
The above discussed and other drawbacks and deficiencies of the prior art are overcome or alleviated by a method for preparing a computer memory cell for a data write operation thereto. The memory cell has a cell supply voltage source which is connected at one end to pull-up devices within the memory cell, and is connected at an opposite end to pull-down devices within the memory cell. The memory cell further has a pair of access transistors for selectively coupling the memory cell to a pair of complementary bitlines. In an exemplary embodiment, the method includes adjusting the voltage of the cell supply voltage source from a first voltage value to a second voltage value, the second voltage value being less than the first voltage value. The memory cell is then coupled to the pair of complementary bitlines, thereby facilitating the data write operation. Following the data write operation, the cell supply voltage is restored from the second voltage value back to the first voltage value.
In one embodiment, the first voltage value corresponds to the pull-up devices within the memory cell being coupled to a logic supply voltage VDD, and the pull-down devices within the memory cell being removably coupled to ground. The second voltage value corresponds to the pull-down devices being floated up to a potential above ground, thereby reducing the magnitude of the voltage of the cell supply voltage source. In an alternative embodiment, the first voltage value corresponds to the pull-up devices within the memory cell being removably coupled to a logic supply voltage VDD, and the pull-down devices within the memory cell being coupled to ground. The second voltage value corresponds to the pull-up devices being floated down to a potential below VDD, thereby reducing the magnitude of the voltage of the cell supply voltage source.